| 摘要 |
A LOW RISC (reduced instruction set computer) III microprocessor reduces the number of branches taken during execution of logic, functional, and symbolic programs to increase the efficiency and effectiveness of pipelined execution memory interleave, and reduces the complexity of RISC architectures. The LOW RISC III is a 40-bit, 4-stage pipelined processor which is pipelined with each stage operating synchronously in parallel. Pipeline breaks are reduced by moving partial unification and trail checking into hardware, and eliminating many short branches by conditional execution of the various instructions.
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