CMOS inverter stage using additional FET - placed between FETs as diode with gate terminal connected to input terminal

摘要

The CMOS inverter stage has a first FET (5) of a first conducting type and a second FET (6) of a second conducting type, their load paths being connected in series with a voltage supply terminal (2) and a reference potential terminal (4). An input terminal (1) is connected to the gate terminals of both transistors. An output terminal (3) is connected to the node of the load paths of the transistors. Third and fourth transistors (7,8) can have their load paths connected between the input and the output terminal and their gate terminals to the input terminal. ADVANTAGE - Switching time considerably reduced.