发明名称 High voltage MOS transistors with reduced parasitic current gain
摘要 A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer. Using this method, the high concentration of slow diffusing N type antimony or arsenic dopant in the buried layer will not out-diffuse into the N-well region and adversely affect the breakdown voltage between the source or drain and the N-well. The out-diffusing of the phosphorus into the epitaxial layer, however, will merge with the phosphorus diffusion from the top to form a uniform N type concentration in the N-well.
申请公布号 US5218228(A) 申请公布日期 1993.06.08
申请号 US19920849723 申请日期 1992.03.11
申请人 SILICONIX INC. 发明人 WILLIAMS, RICHARD K.;BUSSE, ROBERT W.;BLANCHARD, RICHARD A.
分类号 H01L21/331;H01L21/336;H01L21/74;H01L29/10;H01L29/732;H01L29/78 主分类号 H01L21/331
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