| 摘要 |
The modulator regulates its output to obtain constant envelope. It includes the 1st divider (21) for generating the 1st clock (CLK1) by dividing carrier frequency by N, and applying it to a digital data generator (10), the 2nd divider (22) for generating the 2nd clock (CLK2) by dividing carrier frequency by M, a digital phase delayer (200) for generating the 1st-8th outputs (a-h), seventeen exclusive OR gates (G1-G17), and an adder (90) for generating the 3rd added output (VM3) having a constant envelope.
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