发明名称 Forming via holes in a multilevel substrate in a single step
摘要 A method for forming via holes in a multilayer structure in a single step. The invention includes disposing over a base a first layer comprising first metal lines beneath a first dielectric, disposing over the first layer a second layer comprising second metal lines beneath a second dielectric such that a portion of each first metal line is not beneath any second metal line, and forming via holes which extend through the second dielectric to the second metal lines and through the second dielectric and the first dielectric to the portions of the first metal lines. Thereafter conductive metal can be deposited in the via holes. The method is particularly well suited for fabricating copper/polymer substrates.
申请公布号 US5227013(A) 申请公布日期 1993.07.13
申请号 US19910735572 申请日期 1991.07.25
申请人 MICROELECTRONICS AND COMPUTER TECHNOLOGY CORPORATION 发明人 KUMAR, NALIN
分类号 H01L21/48;H05K1/00;H05K3/00;H05K3/40 主分类号 H01L21/48
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