LOCKING CIRCUIT HELPING THE READ-MODIFY WRITE CYCLE

摘要

The circuit supports read modify write cycle which is for the synchronization of processors in a multiprocessor system without occupation of bus. It includes buffers (B1-B8) for buffering various signals from processors, a buffer control logic (5) for controlling the buffers (B1-B8) according to data strobe, RMW cycle (RMC) and read/write (rd/wr) signals, an interlock control logic (6) for generating various interlock signals, a comparator (8) for generating lock-same signal, and a flag (9) for applying lock set signal to the comparator (8).