CIRCUIT FOR PROCESSING WAIT STATE IN MEMORY ACCESS

摘要

The circuit for processing standby state includes a latch (1) for latching address signal of a processor at low state of processor output signal (CLK) and for sending latched signal to a flip-flop (2) and a multiplexer latch (4), a flip-flop (2) for delaying processor internal address (ADDR) signal by one clock and for outputting the delayed signal to a scan flip-flop (3) a scan flip-flop (3) for selecting input terminals (T1,D) according to state of stand-by signal (IDWAIT), and a multiplexer latch (4) for selecting signal between output signal of the latch and the scan flip-flop accoding to state of stand-by signal (IDWAIT) and for outputting the selected signal to valid address line (I-EA).