| 摘要 |
A programmable logic device in which macrocell register reset time, Tclear, and set time, Tset, are comparable in speed to the combinatorial propagation delay time, Tpd. In setting or resetting the macrocell register, the Set (Reset) signal is applied simultaneously to a clocked master latch in the macrocell register and to an output node. During the Set (Reset) period the slave latch of the macrocell register is disconnected from the output node.
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