DATA MIXING PREVENTING CIRCUIT FOR FIFO MEMORY

摘要

When the address difference between memory read and memory write is within the data cross range, this circuit enables to prevent the data cross by clearing the 1st 1H or lag signal without reading or writting the 1H data. The data cross prevention sec. (705) comprises: a writting input delay sec. (10); a reading input delay sec. (20); an AND gate (A1); a data cross detecting sec. (30); and a write (read) enable signal control sec. (40,50) which cleares the 1st 1H of lag signal and outputs the write (read) enable signal when the address difference is within the data cross range.