Multiplier.

摘要

A sign inverting Booth encoder (51 and 52) included in an encoding circuit (700) generates a control signal designating a partial product having a sign different from that designated by an output signal generated from a conventional Booth encoder (1 and 3). A partial product generating circuit (702) generates a partial product according to the control signal from the encoding circuit. A partial product having a sign inverted or non-inverted is generated from a shifter/inverter circuit (10 and 12). A converting circuit (57) generates three-value redundant binary numbers using a sign inverted partial product and a sign non-inverted partial product as a set. An intermediate sum generating circuit (59) performs a redundant binary addition of the three-value redundant binary numbers to generate a final redundant binary number. A final adding circuit (61) converts the finally generated three-value redundant binary number into an ordinary binary number to generate a product Z of binary numbers X and Y. As a result, a multiplier performing multiplication at a high speed with a smaller number of elements is implemented. <IMAGE>