发明名称 Synchronous delay line.
摘要 <p>The invention relates to a multiple delay line comprising a multiple segment delay line (16) comprising a plurality of delay components (20-50) connected in cascade, each of said delay components producing a respective delay signal (NTAP), wherein said multiple segment delay line receives a periodic signals (PHI1) for delay thereof and wherein the delay provided by each of said delay components is determined by a first control signal (Vref). A first phase detector receives the periodic signals PHI1) and a plurality of signals (TAP2, TAP9, TAP14) each produced by a different delay component, for determining whether there is any phase error between the produced delayed signals (TAP2, TAP9, TAP14) and the periodic signal (PHI1), and produces at least one second control signal (PD, CD, NPU, NCU) indicative of said phase error. Control signal generating means (18) is provided, responsive to at least one second control signal (PD, CD, NPU, NCU), for producing the first control signal (Vref). First signal processing means (64, 66, 68, 70) is provided, responsive to signals (A, B, C) produced by a plurality of said delay components, for producing at least one output signal (D, E, F, G) that is a sub-phase of the periodic signal (PHI1).</p>
申请公布号 EP0609969(A2) 申请公布日期 1994.08.10
申请号 EP19940201143 申请日期 1991.06.28
申请人 ANALOG DEVICES, INCORPORATED 发明人 KOKER, GREGORY T.;TSANG, STEVEN T.
分类号 H03D13/00;G06F1/06;G06F1/10;H03K5/13;H03K5/26;H03L7/00;H03L7/081;H03L7/085;H03L7/089;(IPC1-7):H03K5/15 主分类号 H03D13/00
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