发明名称 PLL circuit having a multiloop, and FM receiving method and apparatus able to utilize the same.
摘要 <p>PLL circuits which have both the merits of the analog phase control, in which the good C/N ratio can be realized, and the merits of the digital phase control, in which the broad-band lock can be performed, and multi-channel FM receiving method and apparatus which are able to utilize the PLL circuit to reduce the influence of the leakage occurring among input signals and suppress the image disturbance. One of the PLL circuits includes: a VCO (43); a pre-scaler (44) for dividing a feedback signal obtained from the VCO (43); a first distributor (45) for distributing the feedback signal to send first and second digital feedback signals (D1, D2); a second distributor (42) for distributing a reference signal to send a digital reference signal (D) and an analog reference signal (A); a digital phase comparator (46) for comparing the digital reference signal (D) and the first digital feedback signal (D1) with each other to send a digital phase error signal; a charge pump (47); a mixer (48) for adding the digital phase error signal to an analog phase error signal, which is obtained by comparing the analog reference signal (A) with the second digital feedback signal (D2) to send a composite phase error signal; and a low-pass filter (49) for eliminating high frequency components from the composite phase error signal to input the resultant signal to the VCO (43). &lt;IMAGE&gt;</p>
申请公布号 EP0622904(A2) 申请公布日期 1994.11.02
申请号 EP19940302694 申请日期 1994.04.15
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 AOYAMA, SYUJI;FUNAHASHI, TAKAO;KUBO, KIYOSHI;OKAWA, YASUHITO;SATO, TAKESHI;TAKAHASHI, HIROSHI
分类号 H03L7/087;(IPC1-7):H03L7/087 主分类号 H03L7/087
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