Method and system of programmable resistive devices with read capability using a low supply voltage

摘要

A Programmable Resistive Device (PRD) memory that can be read under low voltage is disclosed. The PRD includes at least one Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to at least one selector and at least one read selector. The read selector includes at least one read source line (SLR) and/or one read enable (ENR) coupled to a second and/or a third supply voltage lines, respectively. The read selector includes at least one MOS device built by core logic device. The PRE in the at least one PRD cells can be configured to be readable by applying voltages to the first, second, and/or the third voltage supply lines to thereby sense the PRE resistance to a logic state. The programmable resistive element can have at least one element in an OTP, MTP, floating gate device, anti-fuse, or emerging memory such as PCRAM, RRAM, or MRAM, etc.

主权项

1. A Programmable Resistive Device (PRD) memory, comprising:
a plurality of PRD memory cells, at least one of the PRD memory cells including at least:
a Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to an element selector and a read selector;the read selector having an read source input (SLR) and/or a read enable input (ENR) coupled to a second supply voltage line and/or a third supply voltage line, respectively, andwherein the PRE is configured to be readable by applying voltages to the first, second, and/or the third supply voltage lines to conduct current flowing through the PRE to thereby sense the PRE resistance into a logic state.