Resistive memory device implementing selective memory cell refresh

摘要

A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

主权项

1. A resistive memory device, comprising:
a two-dimensional array of resistive memory cells, each memory cell being accessed by a word line, a bit line and a source line, each resistive memory cell being configured to store programmed resistance values associated with a first logical state and a second logical state, the difference between a sense signal associated with the first logical state and a sense signal associated with the second logical state forming a sense margin of the resistive memory cell; a first sense amplifier configured to receive a sense signal indicative of a programmed resistance value of a memory cell selected for access and a first reference signal, the first sense amplifier configured to generate a first read signal; a second sense amplifier configured to receive the sense signal indicative of a programmed resistance value of a memory cell selected for access and a second reference signal, the second sense amplifier configured to generate a second read signal, the second reference signal having a reduced sense margin as compared to the first reference signal for the first logical state of the resistive memory cell; a third sense amplifier configured to receive the sense signal indicative of a programmed resistance value of a memory cell selected for access and a third reference signal, the third sense amplifier configured to generate a third read signal, the third reference signal having a reduced sense margin as compared to the first reference signal for the second logical state of the resistive memory cell; a multiplexer configured to receive the second read signal and the third read signal as input signals and to receive the first read signal as a control signal, the multiplexer selecting the second read signal as the output signal in response to the first read signal having the first logical state and the multiplexer selecting the third read signal as the output signal in response to the first read signal having the second logical state; and a comparing circuit configured to receive the first read data and the output signal of the multiplexer and to generate a refresh signal having a first logical state in response to the first read data and the multiplexer output signal having different logical states and having a second logical state in response to the first read data and the multiplexer output signal having the same logical state, wherein for each read operation of a selected memory cell and in response to the refresh signal having the first logical state, the first read signal is written back to the selected memory cell.