| 摘要 |
<p>A data synchronization system (12) for use with a first and a second device has control circuitry (34), first circuitry (36, 38, 40, 42 and 44) and second circuitry (32). The control circuitry generates a first and a second control signal. The logic states of the two control signals depend upon the ratio of the clock frequencies of the two devices. The first circuitry receives a first data signal from the first device and generates a first output signal for the second device depending upon the logic state of the first control signal. Conversely, the second circuitry receives a second data signal from the second device and generates a second output signal for the first device depending upon the logic state of the second control signal. The synchronization system may be incorporated into data processing systems in which the data processor and bus operate at different clock frequencies. <IMAGE></p> |
