A microcontrol unit for a superpipelined, superscalar microprocessor.

摘要

A superscalar, superpipelined microprocessor includes storage circuitry to store an instruction, memory circuitry addressable by a microaddress to output a microinstruction in response to the microaddress, sequencing circuitry coupled to provide the microaddress to the memory circuitry, and decode circuitry coupled to the storage circuitry to detect whether the instruction stored in the storage circuitry comprises a single clock instruction, before the memory circuit outputs the microinstruction, and to indicate such a detection to the sequencing circuitry. Features for single microROM support for a dual pipeline architecture and execution of condition dependent instructions over a plurality of execution stages are further included within the microprocessor. <IMAGE>