SEMICONDUCTOR MEMORY DEVICE

摘要

A semiconductor memory device which operates in a page mode comprises a memory cell array including a number of memory cells, each cell having a normal address. The memory cell array is further divided into a number of pages, each page being defined by a page address that represents a number of the memory cells. First and second latch circuit arrays output data corresponding to the first normal address when the device for sensing is sensing data corresponding to the second normal address. The first and second latch circuit arrays are alternatively activated by a latch control signal. Data access delay times for page mode operations are reduced because delay which results from addressing normal address is eliminated.