| 摘要 |
A noise-suppression logic system suppresses a noise signal having a time duration which is less than a predetermined time. A delay circuit has a delay which is equal to the predetermined time. A logic combining circuit is coupled to the system input terminal and to the output terminal of the delay circuit. A R-S latch circuit, having a RESET input terminal, a SET input terminal, and an OUTPUT terminal provides a delayed output signal corresponding to an input signal which has a time duration greater than the predetermined time. A set circuit has a first input terminal coupled to the system input terminal, a second input terminal coupled to the output terminal of the delay circuit, and an output terminal coupled to the SET input terminal of the R-S flip-flop circuit. A reset circuit has a first input terminal coupled through an inverter to the system input terminal, has a second input terminal coupled to the output terminal of the logic combining circuit, and has an output terminal coupled to the RESET input terminal of the R-S flip-flop circuit. A method is provided for logically suppressing a noisy input signal having a time duration which is less than a predetermined time. The method includes delaying the input signal for the predetermined time and combining the input signal with the delayed input signal. A set signal for a RS latch circuit is formed by combining the input signal with the delayed input signal. A reset signal for the RS flip-flop is provided by logically combining the input signal, the delayed input signal, and an inverted input signal. A delayed output signal from the RS latch corresponds to an input signal which has a time duration greater than the predetermined time.
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