发明名称 |
Word line selection circuit for selecting memory cells |
摘要 |
A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to the second decode line group and the second input terminal for selecting the second decode lines in response to the second signal.
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申请公布号 |
US5436868(A) |
申请公布日期 |
1995.07.25 |
申请号 |
US19940258799 |
申请日期 |
1994.06.13 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
SHIN, YASUHIRO;KODAMA, HIDETAKA;KIMURA, TATSUYA |
分类号 |
G11C11/41;G11C8/10;(IPC1-7):G11C13/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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