| 摘要 |
A single queue for controlling a plurality of FIFO registers in a bus to bus interface. Assume that there are a number of FIFO's and that each FIFO has a number of packet sized locations. Then, the queue for controlling these FIFO's can be implemented from memory and pointers. The queue will have a number of slots, one for each packet location in a FIFO, each slot having one number of bits identifying the originating device and another number of bits identifying the set of pointers involved. The result is that a single queue will have a number of pointers to control a number of FIFO's. For a numerical example, assume two FIFO's connecting two data busses, eight devices connected to one bus, and a capacity of sixteen packets for each FIFO. In this case the queue will have sixteen slots and two sets of pointers. Each set has one pointer to identify the place at which data can be entered into the FIFO, and one pointer to identify the place at which data can be read from the FIFO. Each slot will have 4 bits, three to identify the device and one to identify the FIFO. When a pointer advances, it will inspect the one FIFO identifier bit, and continue to advance until it is pointing to its own next slot. Thus, each set of pointers is free to cross over the other set, but one pointer can never cross over the other in the same set.
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