| 摘要 |
forming an insulation film spacer(7) on side wall of a gate electrode(4), forming a 2nd insulation film(8) and a photosensitive film(9) for a contact mask of 1st charge storage electrode thereon; forming a 3rd insulation film(13) for planarization, and forming a photosensitive film for contact mask of bit line; etching the 3rd insulation film(13) to use a 1st plate electrode as an etching barrier, and depositing a 2nd insulation film(15) for a spacer; forming a bit line being in contact with a drain electrode(6'), and a photosensitive film(18) for a contact mask of 2nd charge storage electrode; forming a 6th insulation film(19) after etching a 5th insulation film(17), the 3rd insulation film(13), a 1st charge storage electrode(10) and a 1st dielectric film(11) in turn; and forming a 2nd plate electrode(22) to deposit a 2nd dielectric film(21) of capacitor on a 2nd charge storage electrode.
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