发明名称 VARIABLE SAMPLE RATE ADC
摘要 A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate. The control circuit includes a sigma-delta modulator for sigma-delta modulating the frequency select signal. A randomizer/suppressor circuit, under control of the output of the sigma-delta modulator, receives an input clock signal and adjusts the frequency of the clock signal to produce a noise-shaped clock signal for controlling the oversampling rate of the ADC.
申请公布号 WO9616482(A1) 申请公布日期 1996.05.30
申请号 WO1995US15164 申请日期 1995.11.21
申请人 ANALOG DEVICES, INC. 发明人 WILSON, JAMES;CELLINI, RONALD, A.;SOBOL, JAMES, M.
分类号 H03M3/02;(IPC1-7):H03M3/02 主分类号 H03M3/02
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