LOGIC CELL AND ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY

摘要

The present invention provides for an FPGA integrated circuit having an array of logic cells (10) and interconnect lines (X1, X2, X3) interconnected by programmable switches (24-29), each formed from a nonvolatile memory cell. The logic cell (10) is designed to provide logic or memory functions according to the setting of programmable switches (30-33) within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between wiring segments.