发明名称 |
Phase lock indicator circuit for a high frequency recovery loop |
摘要 |
An improved phase locked indication circuit for a Costas QPSK carrier recovery loop comprises an inphase channel, a quadrature channel and phase error channel each connected to an input of a three input summing circuit through a diode square law multiplier and wherein the error channel signal is filtered by a low pass filter to smooth the signal before being applied to the negative input of the summing circuit to diminish false lock and not locked signals. The locked and not lock conditions are separated one from the other by a large signal to noise ratio.
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申请公布号 |
US5568521(A) |
申请公布日期 |
1996.10.22 |
申请号 |
US19930137244 |
申请日期 |
1993.09.16 |
申请人 |
UNISYS CORPORATION |
发明人 |
WILLIAMS, BRUCE H.;ARBANAS, GLENN A.;GREEFF, ROY E. |
分类号 |
H03L7/087;H03L7/095;H04L27/227;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/087 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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