发明名称 |
METHOD AND APPARATUS FOR DELIVERING INTERRUPTS IN A PROCESSING SYSTEM |
摘要 |
A multiprocessor system includes a number of subprocessor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
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申请公布号 |
CA2178408(A1) |
申请公布日期 |
1996.12.08 |
申请号 |
CA19962178408 |
申请日期 |
1996.06.06 |
申请人 |
TANDEM COMPUTERS INCORPORATED |
发明人 |
ISWANDHI, GEOFFREY I.;BAKER, WILLIAM EDWARD;BUNTON, WILLIAM PATTERSON;CODDINGTON, JOHN DEANE;FOWLER, DANIEL L.;GARCIA, DAVID J.;HINTIKKA, PAUL N.;MEREDITH, SUSAN STONE;MILLER, STEPHEN H.;SONNIER, DAVID PAUL;WATSON, WILLIAM JOEL;WILLIAMS, FRANK A. |
分类号 |
G06F13/14;G06F9/46;G06F9/48;G06F11/18;G06F13/24;G06F15/16;(IPC1-7):G06F13/24 |
主分类号 |
G06F13/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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