Signal generating device using direct digital synthesis

摘要

An apparatus for generating analog signals, comprising at least one monolithic direct digital synthesis (MDDS) circuit producing an analog MDDS output signal and having at least one digital MDDS input for specifying a desired signal characteristic of the MDDS output signal; one clock generating one clock signal coupled to all the MDDS circuits; and a microprocessor executing a computer program that communicates the desired signal characteristics to the MDDS inputs. The MDDS devices operate at a high clock frequency but generate signals with a low frequency, e.g., 60 Hz. The system monitors its outputs and can maintain its output levels under different conditions. Since all of the signals have a common phase reference the relative phase between the different signals can be programmed.