SPLIT-LEVEL HISTORY BUFFER IN A COMPUTER PROCESSING UNIT

摘要

A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the first portion includes a first tagged instruction. A result is generated for the first tagged instruction. A determination whether a second tagged instruction is to be stored in the first portion of the history buffer is made. Responsive to the determination that the second tagged instruction is to be stored in the first portion of the history buffer, the first tagged instruction and the generated result for the first tagged instruction is written to the second portion of the history buffer.

主权项

1. A method comprising:
fetching, by one or more computer processors, a first instruction; tagging, by the one or more computer processors, the first instruction; storing, by the one or more computer processors, the first instruction in an entry of a register file, wherein the register file stores fetched and tagged instructions; fetching, by the one or more computer processors, a second instruction; tagging, by the one or more computer processors, the second instruction; evicting, by the one or more computer processors, the first instruction from the entry of the register file and storing the second instruction in the entry of the register file; responsive to evicting the first instruction, storing, by the one or more computer processors, the first instruction in a first portion of a history buffer; generating, by the one or more computer processors, a result for the first instruction using an execution unit; responsive to generating the result for the first instruction, moving, by the one or more computer processors, the first instruction from the first portion of the history buffer by storing the first instruction including the generated result for the first instruction in a second portion of the history buffer; determining, by the one or more computer processors, whether a third instruction evicts the second instruction from the entry of the register file; and responsive to determining that the third instruction evicts the second instruction from the entry of the register file, storing, by the one or more computer processors, the second instruction in the first portion of the history buffer.