| 发明名称 |
VERIFYING BRANCH TARGETS |
| 摘要 |
Apparatus and methods are disclosed for implementing bad jump detection in block-based processor architectures. In one example of the disclosed technology, a block-based processor includes one or more block-based processing cores configured to fetch and execute atomic blocks of instructions and a control unit configured to, based at least in part on receiving a branch signal indicating a target location is received from one of the instruction blocks, verify that the target location is a valid branch target. |
| 申请公布号 |
US2016378499(A1) |
申请公布日期 |
2016.12.29 |
| 申请号 |
US201514752356 |
申请日期 |
2015.06.26 |
| 申请人 |
Microsoft Technology Licensing, LLC |
发明人 |
Burger Douglas C.;Smith Aaron L.;Gray Jan S. |
| 分类号 |
G06F9/38 |
主分类号 |
G06F9/38 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising a block-based processor, the block-based processor comprising:
one or more processing cores configured to fetch and execute instruction blocks; and a control unit configured to, based at least in part on receiving a branch signal indicating a target location is received from one of the instruction blocks, verify that the target location is a valid branch target. |
| 地址 |
Redmond WA US |
