DECOUPLED PROCESSOR INSTRUCTION WINDOW AND OPERAND BUFFER

摘要

A processor core in an instruction block-based microarchitecture is configured so that an instruction window and operand buffers are decoupled for independent operation in which instructions in the block are not tied to resources such as control bits and operands that are maintained in the operand buffers. Instead, pointers are established among instructions in the block and the resources so that control state can be established for a refreshed instruction block (i.e., an instruction block that is reused without re-fetching it from an instruction cache) by following the pointers. Such decoupling of the instruction window from the operand space can provide greater processor efficiency, particularly in multiple core arrays where refreshing is utilized (for example when executing program code that uses tight loops), because the operands and control bits are pre-validated.

主权项

1. A method for managing instruction blocks in an instruction window disposed in a processor, comprising:
mapping an instruction block including one or more decoded instructions from an instruction cache into the instruction window; allocating resources for the instruction block in which the resources include control bits and operands that are associated with each of the one or more decoded instructions in the instruction block; maintaining one or more pointers among the resources and the one or more decoded instructions in the block; refreshing the instruction block without re-fetching the instruction block from the instruction cache; and reusing the resources by following the one or more pointers.