发明名称 |
Processor structure and method for maintaining and restoring precise state at any instruction boundary |
摘要 |
A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring precise state at any instruction boundary; (3) tracking instruction status to maintain precise state; (4) checkpointing instructions to maintain precise state; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state.
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申请公布号 |
US5649136(A) |
申请公布日期 |
1997.07.15 |
申请号 |
US19950483958 |
申请日期 |
1995.06.07 |
申请人 |
HAL COMPUTER SYSTEMS, INC. |
发明人 |
SHEN, GENE W.;SZETO, JOHN;PATKAR, NITEEN A.;SHEBANOW, MICHAEL C. |
分类号 |
G06F9/312;G06F9/38;G06F11/14;(IPC1-7):G06F11/00 |
主分类号 |
G06F9/312 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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