ATM-Zellenmultiplexeinrichtung zur Reduzierung der Zugriffsgeschwindigkeit für einen FIFO-Speicher

摘要

In time division multiplexing first through N-th input signals, each having a bit rate V and representing successive ATM cells, a multiplexing section (12, 13') multiplexes the first through the N-th input signals and a dummy input signal into a time division multiplexed signal having another bit rate V x (N+1) and comprising first through N-th multiplexed cells and a dummy multiplexed cell. The first through the N-th and the dummy multiplexed cells are derived from the first through the N-th and the dummy input signals, respectively. A controller (16') successively writes valid cells of the first through the N-th multiplexed cells in an FIFO memory (15) as written cells at a writing rate equal to the bit rate V x (N+1) for a writing time interval defined by the first through the N-th multiplexed cells and reads the written cells from the FIFO memory in a first-in first-out order as a read-out signal at a reading rate equal to the bit rate V x (N+1) for a reading time interval defined by the dummy multiplexed cell. A converter (17) converts the read-out signal into a multiplexed output signal having the bit rate V.