Shared memory architecture of graphics frame buffer and hard disk cache

摘要

A shared memory architecture of graphics frame buffer and hard disk cache is presented. The architecture includes a system bus interface, a hard disk controller, a graphics controller, an arbiter, a memory and a shared memory block. The shared memory block is divided into graphics frame buffer memory and hard disk controller cache memory. The arbiter determines the shared memory access priority between the graphics controller and the hard disk controller. By mean of hardware implementation, memories can be shared by the graphics controller and the disk controller. The complexity of the system is reduced and the system performance is enhanced. The overall system cost is decreased.