发明名称 Method for forming minimum area structures for sub-micron CMOS ESD protection in integrated circuit structures without extra implant and mask steps, and articles formed thereby
摘要 A method and resulting structure is disclosed for extending or enlarging the effective volumes of one or more source, drain, and/or emitter regions of integrated circuit structures such as an SCR structure and/or an MOS structure designed to protect an integrated circuit structure from damage due to electrostatic discharge (ESD). The additional effective volume allows the SCR and/or MOS protection devices to handle additional energy from an electrostatic discharge applied, for example, to I/O contacts electrically connected to the SCR protection structure. The additional effective volume is obtained, without additional doping or masking steps, by forming individual deep doped regions or wells, beneath one or more heavily doped source, drain, and emitter regions, at the same time and to the same depth and doping concentration as conventional main P wells and/or N wells which are simultaneously formed in the substrate, whereby no additional masks and implanting steps are needed.
申请公布号 US5728612(A) 申请公布日期 1998.03.17
申请号 US19960684022 申请日期 1996.07.19
申请人 LSI LOGIC CORPORATION 发明人 WEI, HUA-FANG;COLWELL, MICHAEL
分类号 H01L27/02;(IPC1-7):H01L21/823 主分类号 H01L27/02
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