| 摘要 |
FIELD: radio engineering. SUBSTANCE: device has two circuits which operate simultaneously: phase tuning circuit and time tuning circuit. Control of time tuning is provided by time discriminator as well as by phase tuning circuit by means of application clock frequency as divided frequency of controlled oscillator of phase tuning circuit. Receiver has serial circuit of multiplier 1, which input is connected to device input, multiplier 2, gate 18, low-pass filter 3, control gate 4, voltage- controlled oscillator 5, frequency divider 16, phase shifter 6, which input is connected to second input of second multiplier 2. Output of frequency divider 16 is connected to serial circuit of third multiplier 7, which second input is connected to receiver input, fourth multiplier 12, second low-pass filter 13, decision making unit 14, gate 15, which output is connected to second input of frequency divider 16. Third low-pass filter 17 is connected between output of multiplier 2 and decision making unit 14. Output of third multiplier 7 is connected to input of controlled clock oscillator 10 through serial circuit of third gate 19, discriminator 8 and second control gate 9. Output of clock oscillator 10 is connected to input of shift register 11. Output of shift register 11 is connected to inputs of first and fourth multipliers 1 and 12. Two other outputs are connected to inputs of discriminator 8. Second inputs of gates 18, 15, 19 are connected to output of timer 20. EFFECT: decreased synchronization time, simultaneous tuning of carrier phase and time shift of random sequence. 2 dwgl
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