Resettable memory structure

摘要

The structure according to the invention employs a latch circuit without a reset input as a structural unit for memory. The memory structure's input bus is duplicated and the value of the first bus is forced to "0000" and the value of the second bus is forced to "1111". In a reset state the latch circuits are driven transparent so that each memory bit's reset state depends on which of the buses the latch circuit is connected to. The structure according to the invention fulfils the requirement of an arbitrarily selectable reset state while at the same time the memory can be implemented using the smallest possible elements, i.e. latch circuits without reset inputs.