发明名称 PARALLEL PROCESSOR IMPLEMENTATION OF NET ROUTING
摘要 A method for maximizing effectiveness of parallel processing, using multiple processors, to connect pins of a net of an integrated circuit is disclosed. The method requires the pins to be partitioned into sets of pins and the sets of pins to be further partitioned into meta-sets of the sets of pins. The sets and the meta-sets are connected using a minimal spanning tree algorithm, and the connected sets are made to share a pin, thereby ensuring that the whole net is interconnected without creating a loop in the routing. In addition, because the partitions and the sets of partitions average approximately the same number of pins, the work load can easily be balanced between the processors.
申请公布号 WO9837501(A2) 申请公布日期 1998.08.27
申请号 WO1998US02568 申请日期 1998.02.10
申请人 LSI LOGIC CORPORATION 发明人 SCEPANOVIC, RANKO;JONES, EDWIN;ANDREEV, ALEXANDER E.
分类号 G06F17/50 主分类号 G06F17/50
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