发明名称 |
Burst EDO memory address counter |
摘要 |
A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.
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申请公布号 |
US5850368(A) |
申请公布日期 |
1998.12.15 |
申请号 |
US19970922194 |
申请日期 |
1997.09.02 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
ONG, ADRIAN E.;ZAGAR, PAUL S.;WILLIAMS, BRETT L.;MANNING, TROY A. |
分类号 |
G11C8/04;(IPC1-7):G11C8/00 |
主分类号 |
G11C8/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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