发明名称 MULTILAYER CONNECTING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce variations of resistance values and realize connection in low resistance, by a method wherein a via hole is formed by providing a specified restriction to a wiring and a vertical directions. SOLUTION: A multilayer connection is made between an input and output cell 1 and a pad 2 by using two wiring layers S1, S2, and in a portion where the input and output cell 1 is overlaid on the pad 2, a via hole V is formed in an insulation film Z separating the wiring layer S1 from the wiring layer S2 and the wiring layer S1 is coupled to the wiring layer S2, and also each of wiring layers S1, S2 is brought into contact with the input and output cell 1 and the pad 2. The via hole V is formed on a straight line so as to be in parallel to a wiring direction and have an interval of 3μm or more with respect to each other between the input and output cell 1 and the pad 2, so that the wiring layer S1 is coupled to the wiring layer S2. Accordingly, according to a multilayer connecting method, a connection between arbitrary two points by using a plurality of wiring layers can be made with variations of resistance values being reduced and low resistance.
申请公布号 JPH11121614(A) 申请公布日期 1999.04.30
申请号 JP19970284764 申请日期 1997.10.17
申请人 ROHM CO LTD 发明人 HIRAGA NORIAKI
分类号 H01L23/522;H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L23/522
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