Method of polished spacer formation for ultra-small spacer geometries

摘要

A transistor and transistor fabrication method are presented wherein ultra small spacers are formed adjacent sidewall surfaces of a gate conductor. A first dielectric material is deposited over a semiconductor topography. The first dielectric is partially removed to expose a portion of the gate conductor, and a second dielectric material is deposited upon the first dielectric material and the gate conductor. The second dielectric material is anisotropically etched such that the second dielectric material is preferentially removed from substantially horizontal surfaces and retained adjacent substantially vertical surfaces. The first dielectric material is then selectively removed from areas not masked by the second dielectric material. The composite spacers thus formed adjacent sidewall surfaces of the gate conductor are thinner than spacers formed using conventional techniques. Sub-0.25-micron transistors having sidewall spacers formed by the process described herein may be less susceptible to deleterious source-side parasitic resistance than transistors having conventionally formed spacers.