| 摘要 |
A semiconductor device tester and handler interface includes a tester mother board and a handler board. The handler board includes a central area adapted to mount multiple semiconductor devices to be tested by a tester. The tester mother board has a central area, and first and second peripheral groupings of tester contacts fixed in location on the tester mother board. A ring of spaced electrical connectors such as compressible pogo pins on the tester mother board is positioned between the first and the second groupings of tester contacts such that the area of the handler boards available for mounting semiconductor devices is enhanced. This larger area permits testing in parallel of a plurality of semiconductor devices. A non-electrically conductive coplanarity plate is positioned between the tester and handler boards and forms a cavity inboard of the pogo pins for providing a stand-off to allow pogo pin compressions within a fixed range, to provide equal compression of all the pogo pins, to prevent bending or buckling of the boards, and allows dry gas to be flowed against the back side of the handler board during cold temperature testing.
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