发明名称 |
Lattice matched barrier for dual doped polysilicon gates |
摘要 |
<p>The present invention generally provides a layered stack that can be used in a metal oxide semiconductor. In certain embodiments, the layered stack may be a gate stack that can be used in semiconductor devices, such as a complementary metal oxide semiconductor (CMOS) devices. In another embodiment, the layered stack comprises a dual doped layer having a first doped region and a second doped region in contact with each other, a barrier layer located on the dual doped layer and overlapping the first and second doped regions. The barrier layer includes a nitrided metal silicide. This particular embodiment further includes an ancillary conductive layer located on the barrier layer and that includes an ancillary conductive layer metal silicide. <IMAGE></p> |
申请公布号 |
EP0936667(A1) |
申请公布日期 |
1999.08.18 |
申请号 |
EP19990300212 |
申请日期 |
1999.01.12 |
申请人 |
LUCENT TECHNOLOGIES INC. |
发明人 |
KIZILYALLI, ISIK C;MERCHANT, SAILESH MANSINH;ROY, PRADIP KUMAR;VAIDYA, HEM M. |
分类号 |
H01L21/28;H01L29/78;H01L21/8238;H01L27/092;H01L29/49;(IPC1-7):H01L21/823;H01L21/225 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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