发明名称 Clocked flip flop circuit with built-in clock controller and frequency divider using the same
摘要 A clocked master slave flip flop circuit includes a current mirror circuit with a pair of field effect transistors serving as a constant current source, and the field effect transistors are gated by a clock signal and a complementary clock signal; and the clocked master slave flip flop circuit further includes a built-in logic circuits achieving logic functions inverse to each other, and one the built-in logic circuits and the other field effect transistor are connected in series of one of the field effect transistors and in parallel to the other field effect transistor; the logic circuits are responsive to a clock control signal so as to enable the constant current source, and causes the clocked master slave flip flop circuit to change or maintain a data bit stored therein.
申请公布号 US5945858(A) 申请公布日期 1999.08.31
申请号 US19980050350 申请日期 1998.03.31
申请人 NEC CORPORATION 发明人 SATO, MASAHARU
分类号 H03K3/3562;H03K3/356;(IPC1-7):H03K3/356 主分类号 H03K3/3562
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