发明名称 Solid-state image sensing device that performs an A/D conversion operation at high speed
摘要 Provided is a solid-state image sensing device that performs an A/D conversion operation at high speed. A sample-and-hold section 12 included in an A/D converter in a CMOS image sensor includes switches S1a and S1b and capacitor C1 that sample and hold a dark signal during each cycle period, switches S2a and S2b and capacitor C2 that sample and hold a bright signal during an odd-numbered cycle period, and switches S3a and S3b and capacitor C3 that sample and hold a bright signal during an even-numbered cycle period. While a bright signal is held with switch S2b placed in a conducting state, the next bright signal can be sampled by placing switch S3a in a conducting state.
申请公布号 US9473723(B2) 申请公布日期 2016.10.18
申请号 US201414518073 申请日期 2014.10.20
申请人 Renesas Electronics Corporation 发明人 Ueda Kazuhiro;Okura Shunsuke;Morishita Fukashi
分类号 H04N5/378;H03M1/00;H04N5/376;H03M1/66;H04N5/3745;H04N5/357 主分类号 H04N5/378
代理机构 Sughrue Mion, PLLC 代理人 Sughrue Mion, PLLC
主权项 1. A solid-state image sensing device comprising: a plurality of pixel circuits arrayed in a plurality of rows and columns; a row scanning circuit that sequentially selects the rows one by one for one cycle period and causes each pixel circuit in a selected row to output a dark signal and a bright signal; and an A/D converter that is disposed for each column to convert each of the dark and bright signals, which are output from the pixel circuits in the associated columns, to a digital signal; wherein the A/D converter includes a first sample-and-hold circuit that samples and holds a dark signal output from the pixel circuits in the associated column for each cycle period, and second to Mth sample-and-hold circuits (M is an integer of 3 or greater) that are sequentially selected one by one for one cycle period to sample and hold a bright signal output from the pixel circuits in the associated column for a selected cycle period, and wherein the A/D converter converts each of the signals held by the first to Mth sample-and-hold circuits to a digital signal.
地址 Kanagawa JP