发明名称 SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To avoid the illegal circuit copy by mixedly providing an apparent layout pattern of an actual chip incorporating normally on- and normally off- type transistors and dummy circuits different in logic operation. SOLUTION: N1, N2, P1, P2 are n- and p-type transistors usually forming a circuit constituting an NAND gate having inputs A, B and output C, the threshold voltages of N1, P1 are set lower than usual, N1 is set to a normally on-type and P1 is set to a normally off-type to thereby obtain an inverted value of the input B from the output C, irrespective of the value of the input A. The apparent layout pattern of an actual chip provides an NAND gate with inputs A, B and output C but actually a dummy circuit operating as an inverter with inputs A, B and output C can be constituted. It is possible that a circuit analyzed by connecting adequate signals causing a malfunction to the input A of the dummy circuit cannot normally operate.
申请公布号 JP2000040809(A) 申请公布日期 2000.02.08
申请号 JP19980208415 申请日期 1998.07.23
申请人 SEIKO EPSON CORP 发明人 WATANABE MAKOTO;KUBOKAWA MICHIYA
分类号 H01L27/118;H01L21/82;(IPC1-7):H01L27/118 主分类号 H01L27/118
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