| 摘要 |
PROBLEM TO BE SOLVED: To realize a reduction in number of times of refreshing in both a self-refresh mode and a normal operation mode with a small-scale circuit in a DRAM/logic hybrid LSI. SOLUTION: A refreshing interval counting means 4 outputs a timing signal indicating timing of refreshing for a DRAM 2. A refresh address generating means 5 outputs an address signal indicating a memory cell group 1. A phase counter 6 outputs a reference signal according to a cycle of the address indicating the group 1. A phase memory table 7, for example, stores refresh information made of number of skips of the refresh at each group 1 and outputs a refresh information signal according to the refresh information. A phase comparing means 8 outputs a refresh execution request signal when the refresh information signal corresponds to the reference signal. A refresh control means 9 receives an input of the refresh execution request signal and conducts a refreshing operation for the group 1 indicating the address signal.
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