发明名称 BIT MAP DATA GENERATING APPARATUS/METHOD FOR IC TESTER
摘要 PROBLEM TO BE SOLVED: To provide a bit map data generating apparatus and a method for an IC tester, capable of generating bit map data at high speed without reading out data itself recorded in a defect analysis memory. SOLUTION: A defect analysis memory retrieved section 3B of a defect analysis memory section 3A provided in a main body 3 of an IC tester continuously retrieves a changing point in data indicating whether each bit is defective or not, to obtain an address corresponding to the changing point from a defect analysis memory 3C. A bit map data generating section 2B provided in a control device 2 of the IC tester sequentially generates bit map data in accordance with progress of a predetermined address sequence, and further generates a bit map data file by inverting a logic value of the bit map data in accordance with the address obtained by the defect analysis memory retrieval section 3B.
申请公布号 JP2000048595(A) 申请公布日期 2000.02.18
申请号 JP19980210083 申请日期 1998.07.24
申请人 ANDO ELECTRIC CO LTD 发明人 MATSUO YOSHIHIRO
分类号 G01R31/28;G11C29/00;G11C29/44;(IPC1-7):G11C29/00 主分类号 G01R31/28
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