发明名称 SEMICONDUCTOR ELEMENT LINE MANUFACTURING METHOD
摘要 PURPOSE: Metallization structure and method of a semiconductor device are provided to prevent a short circuit between a gate electrode and an interconnection line. CONSTITUTION: The structure includes an insulating layer(22) formed on a semiconductor substrate(21), the first conductive patterns(23a) formed on the insulating layer(22) and each having a relatively smaller upper side, insulating patterns(24a) formed above the respective first conductive patterns(23a) and each having a lower side greater than the upper side of the first conductive pattern(23a), the first impurity region(26) formed in the substrate(21) near the first conductive pattern(23a), sidewall spacers(28) formed on lateral sides of the first conductive pattern(23a) and the insulating pattern(24a), the second impurity region(29) formed in the substrate(21) between the confronting sidewall spacers(28), and the second conductive pattern(31) formed over an entire structure and connected to the impurity regions(26,29). Since the first conductive pattern(23a) acting as the gate electrode has the lateral sides out of the vertical, the second conductive pattern(31) acting as the interconnection line can be hardly touched thereto.
申请公布号 KR100253403(B1) 申请公布日期 2000.04.15
申请号 KR19980000820 申请日期 1998.01.14
申请人 HYUNDAI MICRO ELECTRONICS CO.,LTD. 发明人 LEE, SANG HO
分类号 H01L21/28;H01L21/3205;H01L21/768;H01L23/52;H01L23/522;H01L29/78;(IPC1-7):H01L21/768 主分类号 H01L21/28
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