| 摘要 |
PURPOSE: A circuit for generating multiple clock signals is provided which multiplies an external clock signal N times and delays the external clock signal through N flip-flops based on the multiplied signal to generate multiple clock signals having no phase difference. CONSTITUTION: A circuit for generating multiple clock signals includes a PLL(100), a buffer(200) and a delay unit(300) configured of N delays serially connected. The PLL receives an external clock signal(CLK) and a feedback clock signal(MCLK) to multiply the external clock signal N times and outputs the multiplied signal with the phase of the multiplied signal according with the phase of the clock signal. The buffer buffers the external clock signal according to the inverted output signal of the PLL. The delay unit delays the output signal of the buffer N times according to the output signal of the PDD.
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