| 摘要 |
PROBLEM TO BE SOLVED: To reduce a circuit scale and to reduce current consumption when an erroneous write-in preventive circuit charging a bit line is provided for preventing that a memory cell unnecessary of write-in is erroneously written in due to wiring capacitance between adjacent bit lines in an SRAM using a four Tr(transistor) memory cell. SOLUTION: The erroneous write-in preventive circuit 10 is constituted of N type Trs of Q13-Q18, a P type Tr of a Q19 and diodes D1-D6. Thus, in the erroneous write-in preventive circuit 10, whether or not the bit line is charged according to the potential of the adjacent bit lines is decided, and the bit line of no probability erroneously written in isn't charged, and only the bit line of the probability erroneously written in is charged. Thus, an excess current doesn't flow.
|
