| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can shorten an access time at a continuous read operation in the case of a wrong hit at a register array part. SOLUTION: A register array part 2 is connected via transfer buses TBT1-1 to TBT1-i, TBN2-1 to TBN2-i to a memory cell array 1 provided with a memory cell 11. The register array part 2 has switches 22-1 to 22-(i+j), 23-1 to 23-(i+j), 24-1 to 24-i. Read/write buses RWBT, RWBN are connected to the switches 24-1 to 24-i and, transistors 3-1 to 4-i are connected between local read/write buses LRWBT, LRWBN connected to the RWBT, RWBN and transfer buses TBT1-1 to TBN2-i. At a continuous read operation in the case of a wrong hit, switches 22-j, 23-j, 24-1 are turned on after the transistors 3-i, 4-i are turned on.
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